WD’s Marketing and a closer look at the Features of the new WD Black NVMe
Here we will explore a bit of what the first-page introduction discussed, with a strong emphasis on the new in-house controller and NAND modules.
Here in WD’s marketing, you can see as I mentioned before that the controller and NAND are in-house designs and made to adapt to future usages and scale up as needed for different applications.
As you can see here WD bucks tradition by locating their controller mid-board to allow close to equal length traces to each NAND IC which means that there should be no aberrant latency talking to any of the storage modules. I would be very interested to see how this scales or performs as the units eventually move to dual-sided modules.
Another thing worth mentioning is the power efficiency which is a big talking point for WD/Sandisk as being NVMe 1.3 compliant means great power savings. While this may not be a big deal for desktop users imagine what that will mean for portable devices who live or die (quite literally) by the battery life.
Here you can see how the hardware accelerated architecture within WD’s drives works and relives the normal strain you would have on your system/CPU as the nCache 3.0 offers a nice boost to performance which we will investigate with our benchmarks later.
Here you can see WDs reference material further explaining the Hardware accelerated features and how it helps to relieve the load on your CPU by doing a lot of the work internally to give you better performance. by reducing the load on your system that in turn could lessen power draw in itself as the controller on the WD drive is much better optimized to do this task vs your system doing it via FW communication.
WD’s Tiered Caching as you see here means it can make very quick SLC burst writes to the nCache 3.0 blocks and also writes to the main 3D TLC so that it can ensure sustained high-speed sequential host write operations and actively manage this all with the ASIC which is WD’s in-house controller.
The WD ECC architecture is designed as a multi-gear LDPC (Low-Density Parity Check) which means if all of this is on the controller itself then Gear 1 can be used for high speed lower power than standard BCH ECC implementation. Gear 2/3 would be focused more on error correction with high error correction capabilities once again internal to the WD controller for high bit-error pages. This is supported by other error protections intrinsically offered but what this means as a whole is that a lot of the ECC capabilities are much more efficiently managed by the WD controller vs the constant FW/SW communication in traditional solutions.
Now let’s take a look in the box.